In a field programmable gate array, CMOS static random access memory (SRAM) devices ("cells") are commonly used for controlling the on/off (relatively low resistance/relatively high resistance) conditions of high-current paths of interconnection ("pass") transistors, typically n-channel MOS transistors. Each of these memory cells is addressable (accessible) through a high-current path of at least one separate access transistor-typically the source-drain path of an n-channel MOS transistor. The high-current path (typically, n-channel MOS transistor source-drain path) of each pass transistor controls a connection between a pair of controlled ("application") circuitry devices, such as logic gates, buffers, latches, look-up tables, or a combination of them. These application circuitry devices, together with the SRAM cells (including their access transistors), are typically integrated in an integrated circuit semiconductor silicon chip. The devices thus form a "field programmable gate array", reflecting the fact that they thus form an array which can be interconnected (configured; "programmed") or re-interconnected (reconfigured; "reprogrammed") at will in the field (i.e., long after the chip has been fabricated) in accordance with various desired interconnection patterns, by writing or re-writing the SRAM cells by means of applying suitable binary digital data signal voltages to the cells through their respective access transistors. These data signal voltages are selected so as to configure or reconfigure the states of the respective SRAM cells (i.e., to write or re-write the cells) in accordance with the desired resulting on/off (relatively low resistance/relatively high resistance) conditions of the respective pass transistors. In this way, the application circuitry can be programmed or reprogrammed in the field.
In CMOS technology, each of the SRAM cells is typically formed by a pair of cross-coupled inverters, each inverter formed by p-channel MOS transistor whose source-drain path is connected in series with an n-channel MOS transistor. Thus each SRAM cell contains a total of four transistors in the inverters, plus one or more access transistors. The semiconductor chip area consumed by all the SRAM cells, together with their pass transistors, ordinarily consumes a substantial fraction of the total chip area.
In U.S. Pat. No. 4,821,233, each SRAM cell included a pair of cross-connected CMOS inverters. Each pair of inverters was accessed through a single n-channel MOS access transistor, instead of the more usual balanced configuration using two access transistors, to save semiconductor chip area. Each inverter contained a p-channel MOS transistor in series with an n-channel MOS transistor. The p-channel MOS transistor in one of the inverters in each SRAM cell has a different threshold voltage than that of the p-channel MOS transistor in the other. This use of two different p-channel MOS transistor thresholds was required to ensure that--immediately after power was applied to the chip and hence to the inverters, but before every cell had been written with its correct memory state (appropriate to the desired, properly configured application circuitry)--all the not-yet-properly-written cells would maintain their pass transistors in their off conditions, in order to avoid short-circuits in the application circuitry. This is to say, every cell that had not yet been written in a one-memory-cell-row-at-a-time writing procedure would deliver a low voltage level to the gate of its n-channel MOS pass transistor, whereby such a pass transistor would be in its off condition and hence would not enable a short circuit in the application circuitry insofar as the high-current path of such a pass transistor was concerned. Otherwise, owing to the random initial memory states of the memory cells, and hence the random on/off conditions of the pass transistors, undesirably many short-circuits would likely arise in the application circuitry. The use of these different p-channel MOS transistor thresholds, however, requires an extra photolithographic step ("level") for fabricating the cells, whereby processing yields undesirably are reduced and hence manufacturing costs are increased.
One way to avoid this need for the two different p-channel MOS thresholds is a methodology involving re-writing all the SRAM cells with proper information prior to applying power supply voltage to the application circuitry. However, such a methodology requires either an extra (on-chip) electronic switching device or a separate (off-chip) mechanical switching device for controlling the power supply voltage applied to the application circuitry--the former alternative undesirably dissipating excess power and undesirably introducing an unwanted voltage drop across the on-chip switching device, and the latter alternative being unfriendly to the (human) user. Moreover, in order to change the memory state of a cell from that in which its input terminal (i.e., the terminal connected to the access transistor's high-current path) is originally at a low voltage level to that in which its input terminal is at a high voltage level (that is to say, to change the memory cell's state from "low" to "high", i.e., from "0" to "1"), such a methodology, as well as that of the above-mentioned patent, requires that the channel width-to-length ratio of the access transistor be larger than that of at least one of the n-channel MOS transistors of the SRAM cell, whereby extra semiconductor chip area is undesirably needed for the access transistor.
Therefore, it would be desirable to have a methodology that does not suffer from the foregoing shortcomings.